1. Field of the Invention
The present invention relates to a protection circuit, and more particularly, to an electrostatic discharge (ESD) protection circuit.
2. Background of the Invention
In order to save power, semiconductor circuits require lower and lower operating voltage. As the operating voltages get lower, the effect of electrostatic noise voltages increases. If not curbed, the relatively high electrostatic noise voltages can damage the semiconductor circuits during operation. Accordingly, protection circuits are included in most semiconductor circuits to prevent such damage.
FIG. 1A is a schematic diagram illustrating an example ESD protection circuit structure. Referring to FIG. 1A, the ESD protection circuit structure comprises two ESD protection clamping circuit 130 and 135. The circuit, or circuits to be protected include the integrated circuits 105 and 110, and the interface circuit 120 between the integrated circuits 105 and 110.
The integrated circuit 105 is coupled to the first power source Vdd1 and the first ground terminal GND1. The integrated circuit 110 is coupled to the second power source Vdd2 and the second ground terminal GND2. The interface circuit 120 is configured to interface the first integrated circuit 105 with the second integrated circuit 110 and is electrically coupled to the first power source Vdd1, the first ground terminal GND1, the second power source Vdd2, and the second ground terminal GND2.
If the first power source Vdd1 has an electrostatic noise voltage, then theoretically, the ESD clamping circuit 130 is immediately turned on. The current generated from the electrostatic noise voltage then flows to the first ground terminal GND1 through the ESD clamping circuit 130. Similarly, if the second power source Vdd2 has an electrostatic noise voltage, then the ESD clamping circuit 135 is immediately turned on. The current generated from the electrostatic noise voltage flows to the second ground terminal GND2 through the ESD clamping circuit 135.
Because there is no connection between the Vdd buses and the GND buses, however, ESD current can flow through the interface circuit 120 during an ESD event, which can cause damage to the interface circuit 120. For example, if an ESD event occurs on Vdd1, then current can flow from Vdd1 through interface circuit 120 to the second ground terminal GND2. Similarly, if the second power source Vdd2 experiences an ESD event, then ESD current can flow from the second power source Vdd2 through interface circuit 120 to the first ground terminal GND1. This problem can be overcome by the ESD protection circuit structure illustrated in FIG. 1B.
FIG. 1B is a schematic block circuit diagram showing another example ESD protection circuit structure. Referring to FIG. 1B, the ESD protection circuit structure comprises two ESD protection clamping circuits 130 and 135, and two ESD protection circuits 140 and 145. Wherein, the circuit to be protected includes the integrated circuits 105 and 110, and the interface circuit 120 between the integrated circuits 105 and 110. The ESD protection circuits 140 and 145 are circuits having the same function.
The integrated circuit 105 is coupled to the first power source Vdd1 and the first ground terminal GND1. The integrated circuit 110 is coupled to the second power source Vdd2 and the second ground terminal GND2. The interface circuit 120 is configured to interface the first integrated circuit 105 with the second integrated circuit 110 and is electrically coupled to the first power source Vdd1, the first ground terminal GND1, the second power source Vdd2, and the second ground terminal GND2.
If the first power source Vdd1 experiences an electrostatic noise voltage, then theoretically, the ESD clamping circuit 130 and the ESD protection circuit 140 are immediately turned on. The current generated from the electrostatic noise voltage then flows to the first ground terminal GND1 and to the second power source Vdd2 through the ESD clamping circuit 130 and the ESD protection circuit 140 such that the ESD noise current will not flow through and damage the integrated circuit 105 and/or the interface circuit 120.
Similarly, if the second power source Vdd2 has an electrostatic noise voltage, then the ESD clamping circuit 135 and the ESD protection circuit 140 are immediately turned on. The current generated from the electrostatic noise voltage flows to the second ground terminal GND2 and to the first power source Vdd1 through the ESD clamping circuit 135 and the ESD protection circuit 140, such that the ESD noise current will not flow through and damage the integrated circuit 110 and the interface circuit 120.
Unfortunately, with the design of FIG. 1B, if the number of power supply sources becomes large, then additional connections between power sources and ground terminals are required and the design becomes much more complicated. Accordingly, when the number of the power sources exceeds 2, such as in the structure illustrated in FIG. 1C, then a common power supply ESD bus 190, and a common ground terminal ESD bus 195 can be required. Referring to FIG. 1C, the ESD protection circuit structure comprises three ESD protection clamping circuits 130, 135, and 155, and six ESD protection circuits 160, 165, 170, 175, 180 and 185. The circuits to be protected include the integrated circuits 105, 110, 115, and 125, and the interface circuits 120 and 150 configured to interface the integrated circuits 105, 110, 115, 125.
The integrated circuit 105 is coupled to the first power source Vdd1 and the first ground terminal GND1. The integrated circuit 110 is coupled to the second power source Vdd2 and the second ground terminal GND2. The third integrated circuit 115 is also coupled to the second power source Vdd2 and the second ground terminal GND2. The fourth integrated circuit 125 is coupled to the third power source Vdd3 and the third ground terminal GND3. The interface circuit 120 is electrically coupled to the first power source Vdd1, the first ground terminal GND1, the second power source Vdd2, and the second ground terminal GND2. The second interface circuit 150 is electrically coupled to the second power source Vdd2, the second ground terminal GND2, the third power source Vdd3, and the third ground terminal GND3. The ESD clamping circuits 130, 135, and 155, and the ESD protection circuits 160, 165, 170, 175, 180 and 185, act to protect the integrated circuits 105, 110, 115 and 125, and the interface circuits 120 and 150 in the event of an ESD event on one or more of the power sources Vdd1, Vdd2, and Vdd3. For example, if an ESD event occurs on the first power source Vdd1, then ESD clamping circuit 130 and ESD protection circuit 160 are immediately turned on. The current generated from the ESD event then flows to the first ground terminal GND1 and to the second power source Vdd2 through the ESD clamping circuit 130 and 135, and through the ESD protection circuits 160, 165, 175, and 180. Thus dashed lines 192 and 193 illustrate the flow of current in the event of an ESD event on first power source Vdd1.
Similarly, if an ESD event occurs on second power source Vdd2 or third power source Vdd3, then the ESD clamping circuits 130, 135, and 155 and the ESD protection circuits 160, 165, 170, 175, 180, and 185 would act to protect integrated circuits 105, 110, 115, and 125, and interface circuits 120 and 150 by passing the resulting ESD current around these circuits through the ESD clamping and protection circuits. It will be understood that the ESD buses can be extended in circuits comprising more than three power sources and ground terminals; however, as mentioned, the structure illustrated in FIG. 1C becomes more and more complicated, and requires more area at higher cost, as the number of power supply sources and ground terminals increases.
Often, back-to-back diode strings are used for ESD protection circuits 160, 165, 170, 175, 180, and 185. Back-to-back diode strings provide an easy and effective connection between power sources and ground terminals and the associated ESD bus, e.g. ESD bus 190 and/or 195. Unfortunately, when back-to-back diode strings are used to connect multiple power sources with an ESD bus, such as ESD bus 190, large leakage current can occur when there is a difference between the power supply voltage levels, especially at high temperature. This leakage current will increase power consumption, and in portable devices reduce battery life times. Another issue can be noise coupling that can result when back-to-back diode strings are used.
Accordingly, in other applications, the ESD protection circuits can comprise silicon controlled rectifiers (SCRs) in a back-to-back configuration. SCRs are characterized by low operating voltage and low power. The SCRs include lateral SCRs (LSCRs), and low-voltage trigger SCRs (LVTSCRs).
FIG. 2 is schematic block circuit and cross sectional configurations showing a conventional SCR ESD protection circuit. Here the SCR is a LSCR. The LSCR comprises a positive-channel metal-oxide-semiconductor (PMOS) transistor and an N-well region. Such an SCR can be referred to as a P-type SCR (PSCR). In another example, the LSCR may comprise a negative-channel metal-oxide-semiconductor (NMOS) transistor and a P-well region, which can be referred to as a N-type SCR (NSCR). In order to illustrate the operating theory, an equivalent PMOS transistor diagram is added in the left configuration of FIG. 2, and an equivalent NMOS transistor diagram is added in the right configuration of FIG. 2. These two circuits in FIG. 2 have the same function.
The circuit in the left configuration of FIG. 2 comprises two PSCRs 141a and 143a, wherein the control gate of the PMOS transistor of the PSCR 141a is coupled to the first power source Vdd1, and the control gate of the PMOS transistor of the PSCR 143a is coupled to the second power source Vdd2. Other connection specifics are shown in FIG. 2. While the first power source Vdd1 generates a higher positive electrostatic voltage noise, at this moment the voltage difference between the control gate of the PMOS transistor and the anode (the source of the PMOS transistor) of the PSCR 143a is higher than the threshold voltage of the PMOS transistor. Accordingly, a current path is generated and the first and the second power sources Vdd1 and Vdd2 are connected through the PSCR 143a. Usually, the threshold voltage is 0.4˜2V. For simple descriptions, all threshold voltages described below are 1V unless otherwise specified.
Accordingly, while the second power source Vdd2 generates a higher electrostatic voltage noise, at this moment, the voltage difference between the control gate of the PMOS transistor and the anode (the source of the PMOS transistor) of the PSCR 141a, is higher than the threshold voltage, about 1V, of the PMOS transistor. Accordingly, a current path is generated and the first and the second power sources Vdd1 and Vdd2 are connected through the PSCR 141a such that the current generated from the electrostatic noise voltage will not damage internal circuits.
The circuit in the right configuration of FIG. 2 comprises two NSCRs 141b and 143b, wherein the control gate of the NMOS transistor of the NSCR 141b is coupled to the power source Vss2, and the control gate of the NMOS transistor of the NSCR 143b is coupled to the power source Vss1. Other connection specifics in the circuit are shown in FIG. 2. The source voltages Vss1 and Vss2 are similar to the first and the second power sources Vdd1 and Vdd2. When the power source Vss1 generates a higher positive electrostatic voltage noise, at this moment, the voltage difference between the control gate of the NMOS transistor and the cathode (the source of the NMOS transistor) of the NSCR 141b is higher than the threshold voltage, about 1V, of the NMOS transistor. Accordingly, a current path is generated and the power sources Vss1 and Vss2 are connected through the NSCR 143b such that the current generated from the electrostatic voltage noise will not damage internal circuits. The operating theory of the NSCR 141b is similar to that of the NSCR 143b. Detailed descriptions are not repeated.
Accordingly, in a conventional ESD protection circuit that uses back-to-back SCRs, when the voltage difference between the first power source Vdd1 and the second power source Vdd2 is larger than 1V, the ESD protection circuit is turned on so that, e.g., the integrated circuits 105 and 110, cannot receive correct data from external circuits. Therefore, only when the voltage difference between the first and the second power sources is lower than 1V can the conventional ESD protection circuit be used, or only when multiple ESD protection circuits are connected in series so that the voltage difference between the first and the second power sources is higher than 1V. This limit complicates the design of the circuit. In addition, the series connection of ESD protection circuits will increase area and costs.
For example, referring to the structure configuration of FIG. 2, the control gate of the PSCR 141a is coupled to the first power source Vdd1, and the control gate of the PSCR 143a is coupled to the second power source Vdd2. As a result, N-well regions of these PSCRs 141a and 143a must be separated, and cannot be a same N-well. The structure of NSCRs 141b and 143b has the same issue. This would increase the layout area of the circuit and increase costs.